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Improvement
Don't reference the specific BaseSimpleCPU type in the SimpleThread::htmAbortTransaction method
Unassigned
Gabe Black
Medium
Done
Oct 25, 2021
Nov 30, 2021
Improvement
Eliminate the arch/pcstate.hh switching header file.
Unassigned
Gabe Black
Medium
Done
Jul 25, 2021
Nov 30, 2021
Bug
ticks.fromSeconds rounding to int not always desired
Unassigned
Gabriel Busnot
Medium
Unresolved
Nov 30, 2021
Nov 30, 2021
Improvement
Improvements to Ruby's SimpleNetwork
Unassigned
Tiago Muck
Medium
Unresolved
Feb 24, 2021
Nov 30, 2021
Bug
SimpleNetwork does not fully support virtual networks
Unassigned
Gabriel Busnot
Medium
Done
Jul 8, 2021
Nov 30, 2021
Improvement
Is instruction-level profiling possible with gem5 simulation?
Unassigned
Minho Ha
Highest
Done
Nov 21, 2021
Nov 28, 2021
New Feature
Get test-x86-hello64-dynamic-* tests running on modern x86 systems
Unassigned
Gabe Black
Medium
Unresolved
Nov 24, 2021
Nov 24, 2021
Bug
libgem5 does not build on MacOS due to --as-needed linker flag being passed
Unassigned
Arun Rodrigues
Medium
Unresolved
Nov 19, 2021
Nov 19, 2021
Bug
Cannot cancel downloading resources
Unassigned
Jason Lowe-Power
Medium
Unresolved
Nov 18, 2021
Nov 18, 2021
Task
Improve the gem5 stdlib raised Exceptions
Unassigned
Bobby Bruce
Medium
Unresolved
Jul 1, 2021
Nov 17, 2021
Bug
The Processor must be incorporated after the Cache Hierarchy when running KVM
Unassigned
Bobby Bruce
Medium
Unresolved
Nov 14, 2021
Nov 15, 2021
Bug
The latest GEM5 version does not support prefetcher under CHI protocol
Unassigned
liyichao
Highest
Unresolved
Nov 10, 2021
Nov 10, 2021
Bug
x86 Locked Read-Modify-Write broken with classic caches and multiple timing cores
Unassigned
Austin Harris
High
Unresolved
Oct 21, 2021
Nov 8, 2021
Improvement
Eliminate use of TARGET_ISA in SCons.
Unassigned
Gabe Black
Medium
Unresolved
Sep 14, 2021
Nov 5, 2021
Improvement
Make specifying supported ISA/CPU pairs more explicit.
Unassigned
Gabe Black
Medium
Unresolved
Jul 25, 2021
Nov 5, 2021
Improvement
Make scons able to build multiple ISAs at a time
Unassigned
Gabe Black
Medium
Unresolved
Jul 25, 2021
Nov 5, 2021
Bug
Remove the assumption that there is a "target" ISA from src/python/gem5/*
Unassigned
Gabe Black
High
Unresolved
Oct 25, 2021
Nov 5, 2021
Improvement
Separate the build logic and the mechanism of individual build steps in the SCons build system.
Unassigned
Gabe Black
Medium
Unresolved
Nov 3, 2021
Nov 3, 2021
Task
Add tests for riscv-tests resources
Unassigned
Bobby Bruce
Medium
Unresolved
Nov 3, 2021
Nov 3, 2021
Epic
Enable building more than one ISA into gem5 at a time.
Unassigned
Gabe Black
Medium
Unresolved
Jul 25, 2021
Nov 2, 2021
Epic
arch-riscv: vector architecture model
Unassigned
Cristobal Ramirez Lazo
Medium
Unresolved
Jun 2, 2020
Nov 1, 2021
Improvement
Allow partially pipelined functional units
Unassigned
Fisher Xue
Medium
Unresolved
Oct 28, 2021
Oct 28, 2021
Bug
The RISCV disk image does not contain m5 utilities
Unassigned
Bobby Bruce
Medium
Done
Sep 1, 2021
Oct 27, 2021
Task
Alter the RISCV disk image resource to auto-login on boot
Unassigned
Bobby Bruce
Medium
Done
Sep 1, 2021
Oct 27, 2021
Task
Create RISCV boot-exit tests
Unassigned
Bobby Bruce
Medium
Unresolved
Sep 1, 2021
Oct 27, 2021
Task
Add a `exit.sh` script to the RISCV disk image
Unassigned
Bobby Bruce
Medium
Done
Sep 1, 2021
Oct 27, 2021
Task
Setup the RISCV disk image to run `m5 readfile` after booting
Unassigned
Bobby Bruce
Medium
Done
Sep 1, 2021
Oct 27, 2021
Task
The X86 boot exit test should be refactored to run any command on boot, not just `m5 exit`
Unassigned
Bobby Bruce
Medium
Done
Sep 1, 2021
Oct 27, 2021
Bug
Gem5 tests don't seem to check the return code of the simulation
Unassigned
Davide Basilio Bartolini
Highest
Done
Sep 28, 2021
Oct 27, 2021
Task
Boards currently have the linux kernel `root` parameter hardcoded. This is not always correct. Come up a solution for this
Unassigned
Bobby Bruce
Medium
Unresolved
Oct 13, 2021
Oct 27, 2021
Improvement
TimingCPU with classic memory (2CPU, init/systemd) system fails
Unassigned
Ayaz Akram
Low
Unresolved
Feb 20, 2020
Oct 27, 2021
Bug
KVM Mode does not function in the Component Library SimpleProcessor.
Unassigned
Bobby Bruce
Medium
Done
Jul 1, 2021
Oct 26, 2021
Improvement
Eliminate the arch/decoder.hh switching header file.
Unassigned
Gabe Black
Medium
Unresolved
Jul 25, 2021
Oct 25, 2021
Epic
Implement a multi-Level TLB hierarchy
Unassigned
Giacomo Travaglini
Medium
Done
Oct 1, 2020
Oct 25, 2021
Improvement
Allow Arm TLBs to store partial entries
Unassigned
Giacomo Travaglini
Medium
Unresolved
Oct 25, 2021
Oct 25, 2021
Epic
Eliminate switching header files
Unassigned
Gabe Black
Medium
Unresolved
Jul 25, 2021
Oct 25, 2021
Improvement
Eliminate the arch/page_size.hh switching header file.
Unassigned
Gabe Black
Medium
Done
Jul 25, 2021
Oct 22, 2021
Task
Migrate configs from gem5 resources to configs/example/gem5_library/; translate to use the gem5 library
Unassigned
Bobby Bruce
Medium
Unresolved
Oct 19, 2021
Oct 20, 2021
Epic
Develop a model/component library in pure python
Unassigned
Jason Lowe-Power
Medium
Unresolved
Jun 26, 2020
Oct 19, 2021
New Feature
Is gem5 importable from python?
Unassigned
david mlw
Medium
Done
Oct 8, 2021
Oct 18, 2021
Task
Create an ISA-agnotic method to obtain gem5 resource from the gem5 library
Unassigned
Bobby Bruce
Medium
Unresolved
Oct 14, 2021
Oct 14, 2021
Task
Add documentation discussing how to setup KVM on your machine
Unassigned
Bobby Bruce
Low
Unresolved
Jul 14, 2020
Oct 13, 2021
Bug
32 bit syscalls cause segfault
Unassigned
Jason Lowe-Power
Medium
Done
Aug 30, 2021
Oct 13, 2021
Improvement
Implement POSIX syscalls with "at" suffix
Unassigned
Giacomo Travaglini
Medium
Done
Sep 28, 2021
Oct 13, 2021
Bug
ARM SE mode: Cannot access file (RISCV runs OK)
Unassigned
Rohit Singh
Medium
Done
Sep 20, 2021
Oct 12, 2021
Bug
Fix-sized MessageBuffer delayed enqueuing behaves unexpectedly
Unassigned
Gabriel Busnot
Medium
Unresolved
Oct 8, 2021
Oct 8, 2021
Epic
Model DVM messages for TLBIs and DSBs accurately on Arm
Unassigned
Samuel Stark
Medium
Unresolved
Sep 24, 2021
Oct 4, 2021
Improvement
Eliminate the arch/isa.hh switching header file.
Unassigned
Gabe Black
Medium
Unresolved
Jul 25, 2021
Oct 2, 2021
Task
Figure out how best to distribute the gem5 compents library with gem5
Unassigned
Bobby Bruce
Medium
Done
Jul 1, 2021
Sep 29, 2021
Bug
DerivO3CPU model hangs when resume from a checkpoint
Unassigned
Luming Wang
Highest
Done
Sep 12, 2021
Sep 29, 2021
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