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Bug
Bug with fstat(0) on x86_64, se mode
Unassigned
Danila Borisov
Low
Done
Jan 30, 2023
Jan 30, 2023
Bug
Nightly tests failing due to timeout
Unassigned
Bobby Bruce
High
Unresolved
Dec 1, 2021
Jan 27, 2023
Improvement
Create documentation for stdlib
Unassigned
Jason Lowe-Power
Medium
Unresolved
Jan 25, 2023
Jan 25, 2023
Bug
ALL/gem5.debug with sanitizers does not link on x86_64
Unassigned
Gabriel Busnot
Medium
Done
Jan 24, 2023
Jan 25, 2023
Bug
tcmalloc triggers asan
Unassigned
Gabriel Busnot
Medium
Unresolved
Jan 18, 2023
Jan 20, 2023
Bug
When setting 'AuthenticAMD' as the cores' vendor string, X86 linux boot takes long time due to trying to (and failing to) detect more than 1 cpu.
Unassigned
Bobby Bruce
Medium
Unresolved
Nov 10, 2022
Jan 12, 2023
Bug
Dynamically linked app failed in SE mode for RISC-V
Unassigned
Maxim Andronov
Medium
Unresolved
Dec 21, 2022
Jan 12, 2023
Bug
AMDGPU GCN3 --FunctionalTLB bug
Unassigned
Qun Liu
Medium
Unresolved
Nov 18, 2022
Jan 9, 2023
New Feature
Implement RV32 Model
Unassigned
Roger Chang
Medium
Done
Jan 5, 2023
Jan 5, 2023
New Feature
Support for Arm's SME v1 architecture extension
Unassigned
Sascha Bischoff
Medium
Unresolved
Oct 4, 2022
Jan 5, 2023
Bug
CopyEngine configuration
Unassigned
Qun Liu
Medium
Unresolved
Jan 4, 2023
Jan 4, 2023
Bug
m5ops not working on GPU-FS simulation
Unassigned
Rajesh Shashi Kumar
Medium
Done
Dec 7, 2022
Dec 30, 2022
Bug
Debug flags breaks GPU-FS square simulation
Unassigned
Rajesh Shashi Kumar
Medium
Done
Dec 6, 2022
Dec 29, 2022
Bug
GEM5 arguments tokenizing inappropriately in se mode (using se.py) when using bash script to run
Unassigned
Kassie Povinelli
Medium
Unresolved
Dec 9, 2022
Dec 29, 2022
Task
Fix/Refactor the stdlib workload interface
Unassigned
Bobby Bruce
Medium
Unresolved
Nov 8, 2022
Dec 29, 2022
Bug
Stdlib hello example segfaults if num_cores is not 1
Unassigned
Rongcui Dong
Medium
Unresolved
Nov 23, 2022
Dec 29, 2022
Improvement
Implement x86 instructions to run spec2006 (SSE 4.1)
Unassigned
Danila Borisov
Medium
Unresolved
Dec 16, 2022
Dec 29, 2022
Task
Create v22.0 Release notes
Unassigned
Bobby Bruce
Medium
Done
Mar 17, 2022
Dec 22, 2022
Bug
SystemCall Debug-flag and stats numSyscalls does not work
Unassigned
Qun Liu
Medium
Unresolved
Oct 7, 2022
Dec 21, 2022
Bug
Incorrect restoring of memory mapped files (VMA) from checkpoint
Unassigned
Emin Gadzhiev
High
Done
Nov 21, 2022
Dec 15, 2022
Bug
scons: CheckPythonLib fails if using python-config.py
Unassigned
Adrian Herrera
Low
Unresolved
Sep 6, 2022
Dec 7, 2022
Sub-task
Modify gem5 to pass an object upon an on an exit event instead of a string
Unassigned
Bobby Bruce
Medium
Unresolved
Dec 10, 2021
Dec 6, 2022
Task
Move general stats to BaseCPU
Unassigned
Jasjeet Rangi
Medium
Unresolved
Nov 23, 2022
Nov 23, 2022
Bug
Gem5 unittests and system-level tests doesn't work
Unassigned
Chengyong Zhong
Medium
Unresolved
Nov 3, 2022
Nov 15, 2022
Task
Creating new Resource types
Unassigned
Melissa Jost
Medium
Unresolved
Oct 11, 2022
Nov 8, 2022
Bug
Building problem on WSL2: cannot find HDF5 lib and png.h
Unassigned
tyskink
Medium
Unresolved
Nov 7, 2022
Nov 7, 2022
Bug
RISC-V + Ruby + C++ Threads cause segfault on SE
Unassigned
Rongcui Dong
Medium
Unresolved
Nov 2, 2022
Nov 3, 2022
Bug
Build fails with Python 3.11 due to pybind11
Unassigned
Adrian Herrera
High
Unresolved
Nov 2, 2022
Nov 2, 2022
Bug
Gem5 cxx mode is about 50% slower than python mode
Unassigned
yunlong cai
Medium
Unresolved
Oct 14, 2022
Oct 14, 2022
Oct 15, 2022
Bug
GPU_VIPER fails to compile
Unassigned
Gautam Pathak
Medium
Unresolved
Sep 24, 2022
Oct 12, 2022
Bug
X86-based ELFie cannot run in gem5
Unassigned
Yicheng Wang
Highest
Unresolved
Oct 9, 2022
Oct 9, 2022
Nov 11, 2022
New Feature
Pre-built board with a RISC-V ISA
Unassigned
Kunal Pai
Medium
Done
Aug 1, 2022
Oct 7, 2022
Bug
Remote GDB not working after switching CPU
Unassigned
Jonas Juffinger
High
Unresolved
Oct 6, 2022
Oct 6, 2022
Bug
pymongo >=4 removes disable_md5 argument from GridFSBucket
Unassigned
Kyle Roarty
Medium
Unresolved
Sep 30, 2022
Oct 4, 2022
Bug
GenericTimerFrame nonSecureAccess not instantiated
Unassigned
Heng Zhuo
Medium
Unresolved
Sep 24, 2022
Oct 4, 2022
Bug
SMT simulation in x86 is not supported
Unassigned
Abhishek Singh
Medium
Unresolved
Feb 11, 2020
Oct 3, 2022
Bug
Baremetal testcase on 16 cores with O3 CPU and Exclusive cluster L3 cache(4 cores per cluster) has CHI invalid transition
Unassigned
Boyao Wang
High
Unresolved
Jul 7, 2022
Sep 30, 2022
Improvement
Add Control Type Instructions to MinorCPU Stats
Unassigned
Kunal Pai
Medium
Done
Sep 1, 2022
Sep 12, 2022
Bug
Fix: No suitable back trace implementation found.
Unassigned
Ryan Gambord
Lowest
Unresolved
Sep 9, 2022
Sep 9, 2022
Bug
build gem5.opt V22.0.0.2
Unassigned
Qun Liu
Medium
Unresolved
Aug 11, 2022
Sep 5, 2022
Bug
Unused RAS for RISC-V
Unassigned
gk c
Medium
Done
Jun 21, 2021
Sep 2, 2022
Epic
Eliminate switching header files
Unassigned
Gabe Black
Medium
Done
Jul 25, 2021
Sep 2, 2022
Improvement
Eliminate the arch/isa.hh switching header file.
Unassigned
Gabe Black
Medium
Done
Jul 25, 2021
Sep 2, 2022
Improvement
Eliminate the arch/vecregs.hh switching header file
Unassigned
Gabe Black
Medium
Done
Jul 25, 2021
Sep 2, 2022
Epic
Enable building more than one ISA into gem5 at a time.
Unassigned
Gabe Black
Medium
Done
Jul 25, 2021
Sep 2, 2022
Improvement
Eliminate use of TARGET_ISA in SCons.
Unassigned
Gabe Black
Medium
Done
Sep 14, 2021
Sep 2, 2022
Improvement
Make specifying supported ISA/CPU pairs more explicit.
Unassigned
Gabe Black
Medium
Done
Jul 25, 2021
Sep 2, 2022
Improvement
Make scons able to build multiple ISAs at a time
Unassigned
Gabe Black
Medium
Done
Jul 25, 2021
Sep 2, 2022
Bug
m5_read_file does not return correct result with O3CPU
Unassigned
Jiajie Chen
Medium
Done
Aug 21, 2022
Sep 1, 2022
Task
Add error if Options.py is used in conjunction with stdlib
Unassigned
Jason Lowe-Power
Medium
Unresolved
Sep 1, 2022
Sep 1, 2022
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