Through this Epic, we will define a model library for gem5. Eventually, we will provide validation information for all of these models.

More information coming soon.

Link to a design document:

Some high-level tasks

• Develop abstract “base” classes for sub systems (e.g., caches) and define the interfaces between them.

• Develop a few example sets of components based off of gem5-resources x86 full system examples

  • Single core CPU with parameterizable cache hierarchy

    • Two level classic

    • Three level classic with private l1/l2

    • Two different Ruby hierarchies

  • Extend to parameterize the number of CPUs

    • 1,2,4,8,16

  • Extend to parameterize the DRAM

    • 1 channel

    • 2 channel

    • Different possible devices

• Run (some) of the above configurations with the gem5-resources and publicize the results