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Bug
A bug in rcr instruction in x86
Unassigned
Youngin Kim
Medium
Unresolved
Aug 9, 2022
Aug 9, 2022
Improvement
Improving parsing stats
Unassigned
Mahyar Samani
Medium
Unresolved
Aug 8, 2022
Aug 8, 2022
Improvement
Improving pystats interface
Unassigned
Mahyar Samani
Medium
Unresolved
Aug 8, 2022
Aug 8, 2022
Bug
Broken CSS for gem5-website
Unassigned
Mahyar Samani
Medium
Unresolved
Aug 3, 2022
Aug 3, 2022
Task
Add tests for HBM2
Unassigned
Ayaz Akram
Medium
Unresolved
Aug 1, 2022
Aug 1, 2022
Task
HBM2 stack component in stdlib
Unassigned
Ayaz Akram
Medium
Unresolved
Aug 1, 2022
Aug 1, 2022
Improvement
Extend stdlib to take and create exit events for Simpoints
Unassigned
Zhantong
Medium
Unresolved
Aug 1, 2022
Aug 1, 2022
New Feature
Basic Block Vector Generation within gem5 for SimPoints
Unassigned
George Zaets
Medium
Unresolved
Aug 1, 2022
Aug 1, 2022
New Feature
Pre-built board with a RISC-V ISA
Unassigned
Kunal Pai
Medium
Unresolved
Aug 1, 2022
Aug 1, 2022
Bug
CHI system - Intermediate L3$ between L2$ and LLC does not record all hits/misses for Clean Unique requests
Unassigned
Javed Osmany
Medium
Unresolved
Aug 1, 2022
Aug 1, 2022
Bug
SystemC multi_passthrough_sockets cannot be bound hierarchically
Unassigned
Derek Christ
Medium
Done
Jul 26, 2022
Aug 8, 2022
Bug
Fail to restore checkpoint using SE mode
Unassigned
Xuefeng
Highest
Unresolved
Jul 25, 2022
Jul 25, 2022
Jul 27, 2022
Task
Create a Python script in the gem5-resources repo to add an entry to resources.json
Unassigned
Bobby Bruce
Medium
Unresolved
Jul 25, 2022
Jul 25, 2022
Task
Consider moving the gem5 resources JSON file to a key-value pair structure
Unassigned
Bobby Bruce
Medium
Unresolved
Jul 25, 2022
Jul 25, 2022
Task
Add "workload" type to encapsulate workload runs
Unassigned
Bobby Bruce
Medium
Unresolved
Jul 25, 2022
Jul 25, 2022
Task
Move gem5-art 'artifact' fields to the gem5-resource's Jason
Unassigned
Bobby Bruce
Medium
Unresolved
Jul 25, 2022
Jul 25, 2022
Epic
The gem5-resources should be re-visited and altered for the needs of the gem5 project.
Unassigned
Bobby Bruce
Medium
Unresolved
Jul 25, 2022
Jul 25, 2022
Task
Incorporate Multi-ISA work
Unassigned
Bobby Bruce
Medium
Unresolved
Jul 25, 2022
Jul 25, 2022
Task
Create an stdlib ViperBoard for GPU simulation
Unassigned
Bobby Bruce
Medium
Unresolved
Jul 25, 2022
Jul 25, 2022
Task
Enable the running of multiple simulations via a single configuration script
Unassigned
Bobby Bruce
Medium
Unresolved
Jul 25, 2022
Jul 25, 2022
Sub-task
Simulate to a warmup
Unassigned
Bobby Bruce
Medium
Unresolved
Jul 25, 2022
Jul 25, 2022
Bug
Fail to restore checkpoint using SE mode
Unassigned
Xuefeng
High
Unresolved
Jul 24, 2022
Jul 24, 2022
New Feature
x86 bulk cache operations (wbinvd, wbnoinvd, invd)
Unassigned
Eliot Moss
Low
Unresolved
Jul 23, 2022
Jul 23, 2022
Improvement
Extend `set_se_binary_workload` function to allow passing of binary parameters
Unassigned
Bobby Bruce
Medium
Unresolved
Jul 22, 2022
Jul 22, 2022
Bug
Unable to open files when restoring from checkpoints
Unassigned
Haochen Gong
Medium
Unresolved
Jul 20, 2022
Jul 22, 2022
Bug
Switching from multiple non-KVM cores is broken
Unassigned
Bobby Bruce
Medium
Unresolved
Jul 20, 2022
Jul 20, 2022
Bug
`debugfaults.hh:128: panic: Invalid microop!` returns when switching to minor CPU from non-kvm CPU
Unassigned
Bobby Bruce
Medium
Done
Jul 20, 2022
Jul 20, 2022
Bug
Generate program fragments through gem5 (ARM64)+simpoint+benchmark and run these fragments
Unassigned
刘利华
Medium
Unresolved
Jul 13, 2022
Jul 13, 2022
Bug
Failed to build gem5 on MacOS Intel x86
Unassigned
Liu Yihua
Medium
Unresolved
Jul 8, 2022
Jul 8, 2022
Bug
Baremetal testcase on 16 cores with O3 CPU and Exclusive cluster L3 cache(4 cores per cluster) has CHI invalid transition
Unassigned
Boyao Wang
High
Unresolved
Jul 7, 2022
Jul 7, 2022
Improvement
The Simulator module (stdlib) should output explicit statements outlining default EXIT_EVENT behavior
Unassigned
Bobby Bruce
Medium
Done
Jul 6, 2022
Jul 12, 2022
Bug
Suspicious SnpResp expected count in Send_SnpCleanInvalid_NoReq
Unassigned
Gabriel Busnot
Medium
Done
Jul 5, 2022
Jul 5, 2022
Bug
SystemC end_of_simulation() callback not called at the end of the simulation
Unassigned
Derek Christ
Medium
Unresolved
Jun 30, 2022
Jun 30, 2022
Bug
/ARM/gem5.opt booting vmlinux.arm64 bug
Unassigned
Qun Liu
Medium
Unresolved
Jun 29, 2022
Jul 26, 2022
New Feature
x86 "serialize" instruction
Unassigned
Eliot Moss
Low
Done
Jun 27, 2022
Jul 23, 2022
Bug
The recovery program reports a segmentation fault from the checkpoint point
Unassigned
刘利华
Medium
Unresolved
Jun 27, 2022
Jun 27, 2022
Bug
Instructions are issued to only one cpu in a 2CPU multicore design/Gem5
Unassigned
Jwan Ali
Medium
Done
Jun 25, 2022
Jul 25, 2022
Bug
Minor/RV64 execute.cc: "panic: ... commit from a suspended thread ..."
Unassigned
Ang Li
High
Unresolved
Jun 18, 2022
Jun 18, 2022
Bug
memoryorder violations of O3 cpu out of order lead to fatal error
Unassigned
sasehbh
Medium
Unresolved
Jun 14, 2022
Jun 14, 2022
Bug
Incorrect byte swapping logic: Loses fractional value for floating-point accesses
Unassigned
Austin Chase Minor
Medium
Unresolved
Jun 1, 2022
Jul 1, 2022
Improvement
Improving the ArmBoard
Unassigned
Kaustav Goswami
Medium
Unresolved
May 31, 2022
Jul 6, 2022
Bug
Unable to build on wsl2 win11
Unassigned
Zhibin Yang
Medium
Done
May 16, 2022
Jul 7, 2022
Bug
SystemC within gem5 and macOS
Unassigned
Matthias Jung
Medium
Unresolved
May 10, 2022
May 10, 2022
New Feature
Require new bootloader for the VExpress_GEM5_Foundation platform
Unassigned
Giacomo Travaglini
Medium
Done
May 9, 2022
May 9, 2022
Bug
CHI assertion firing when HNF/L3$ clusivity set to "Mostly Exclusive"
Unassigned
Javed Osmany
High
Unresolved
May 6, 2022
May 6, 2022
Sub-task
RAS cannot be properly processed in branch predictor when both isCall and isReturn are set (in RISC-V)
Unassigned
Jin Cui
Lowest
Unresolved
May 5, 2022
May 9, 2022
Bug
Weekly tests failing with 2-core Timing X86 boot with MesiTwoLevel
Unassigned
Bobby Bruce
Medium
Unresolved
May 3, 2022
Jul 6, 2022
Bug
gem5_within_systemc broken again
Unassigned
Lukas Steiner
Medium
Unresolved
Apr 25, 2022
May 13, 2022
Bug
8-core X86 Weekly Boot Tests are failing for Atomic and Timing Cores with Classic and MI_Example Cache hierarchies
Unassigned
Bobby Bruce
Medium
Unresolved
Apr 11, 2022
Jul 6, 2022
Bug
MI_Example with Timing CPU X86 Weekly Boot tests are failing
Unassigned
Bobby Bruce
Medium
Unresolved
Apr 11, 2022
Jul 6, 2022
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