| | ticks.fromSeconds rounding to int not always desired | | | | | Unresolved | Nov 30, 2021 | Nov 30, 2021 | | |
| | Get test-x86-hello64-dynamic-* tests running on modern x86 systems | | | | | Unresolved | Nov 24, 2021 | Nov 24, 2021 | | |
| | Is instruction-level profiling possible with gem5 simulation? | | | | | Done | Nov 21, 2021 | Nov 28, 2021 | | |
| | libgem5 does not build on MacOS due to --as-needed linker flag being passed | | | | | Unresolved | Nov 19, 2021 | Nov 19, 2021 | | |
| | Cannot cancel downloading resources | | | | | Unresolved | Nov 18, 2021 | Nov 18, 2021 | | |
| | The Processor must be incorporated after the Cache Hierarchy when running KVM | | | | | Unresolved | Nov 14, 2021 | Nov 15, 2021 | | |
| | The latest GEM5 version does not support prefetcher under CHI protocol | | | | | Unresolved | Nov 10, 2021 | Nov 10, 2021 | | |
| | Separate the build logic and the mechanism of individual build steps in the SCons build system. | | | | | Unresolved | Nov 3, 2021 | Nov 3, 2021 | | |
| | Add tests for riscv-tests resources | | | | | Unresolved | Nov 3, 2021 | Nov 3, 2021 | | |
| | Allow partially pipelined functional units | | | | | Unresolved | Oct 28, 2021 | Oct 28, 2021 | | |
| | Allow Arm TLBs to store partial entries | | | | | Unresolved | Oct 25, 2021 | Oct 25, 2021 | | |
| | Remove the assumption that there is a "target" ISA from src/python/gem5/* | | | | | Unresolved | Oct 25, 2021 | Nov 5, 2021 | | |
| | Don't reference the specific BaseSimpleCPU type in the SimpleThread::htmAbortTransaction method | | | | | Done | Oct 25, 2021 | Nov 30, 2021 | | |
| | x86 Locked Read-Modify-Write broken with classic caches and multiple timing cores | | | | | Unresolved | Oct 21, 2021 | Nov 8, 2021 | | |
| | Migrate configs from gem5 resources to configs/example/gem5_library/; translate to use the gem5 library | | | | | Unresolved | Oct 19, 2021 | Oct 20, 2021 | | |
| | Create an ISA-agnotic method to obtain gem5 resource from the gem5 library | | | | | Unresolved | Oct 14, 2021 | Oct 14, 2021 | | |
| | Boards currently have the linux kernel `root` parameter hardcoded. This is not always correct. Come up a solution for this | | | | | Unresolved | Oct 13, 2021 | Oct 27, 2021 | | |
| | Is gem5 importable from python? | | | | | Done | Oct 8, 2021 | Oct 18, 2021 | | |
| | Fix-sized MessageBuffer delayed enqueuing behaves unexpectedly | | | | | Unresolved | Oct 8, 2021 | Oct 8, 2021 | | |
| | Gem5 tests don't seem to check the return code of the simulation | | | | | Done | Sep 28, 2021 | Oct 27, 2021 | | |
| | Implement POSIX syscalls with "at" suffix | | | | | Done | Sep 28, 2021 | Oct 13, 2021 | | |
| | Model DVM messages for TLBIs and DSBs accurately on Arm | | | | | Unresolved | Sep 24, 2021 | Oct 4, 2021 | | |
| | Improve and expand the resources.json file in the gem5 resources repository | | | | | Unresolved | Sep 23, 2021 | Sep 23, 2021 | | |
| | CHI assertion error when L2 Cache configured as shared cache | | | | | Unresolved | Sep 23, 2021 | Sep 23, 2021 | | |
| | Update gem5's option parser in python/m5/main.py and python/m5/options.py to argparse | | | | | Unresolved | Sep 20, 2021 | Sep 20, 2021 | | |
| | ARM SE mode: Cannot access file (RISCV runs OK) | | | | | Done | Sep 20, 2021 | Oct 12, 2021 | | |
| | Add support on glibc2.33 systemcall newfstatat() | | | | | Unresolved | Sep 18, 2021 | Sep 21, 2021 | | |
| | scons failed to buiild gem5 before git-hooks installed | | | | | Done | Sep 18, 2021 | Sep 18, 2021 | | |
| | gem5art-run check_failure feature limitations with celery | | | | | Unresolved | Sep 15, 2021 | Sep 16, 2021 | | |
| | kernel panic when restore DerivO3CPU with KVM checkpoint | | | | | Unresolved | Sep 14, 2021 | Sep 17, 2021 | | |
| | Eliminate use of TARGET_ISA in SCons. | | | | | Unresolved | Sep 14, 2021 | Nov 5, 2021 | | |
| | DerivO3CPU model hangs when resume from a checkpoint | | | | | Done | Sep 12, 2021 | Sep 29, 2021 | | |
| | KVM to Timing CPU switching does not function properly in the gem5 library | | | | | Done | Sep 10, 2021 | Sep 22, 2021 | | |
| | The PARSEC benchmark tests fail for MESI_TwoLevel [gem5 library] | | | | | Unresolved | Sep 7, 2021 | Sep 7, 2021 | | |
| | Merge the gem5art library into the more general "gem5 library" (formallly "gem5 components") | | | | | Unresolved | Sep 3, 2021 | Sep 3, 2021 | | |
| | Add default value for `Root.sim_quantum` | | | | | Unresolved | Sep 3, 2021 | Sep 3, 2021 | | |
| | The X86 boot exit test should be refactored to run any command on boot, not just `m5 exit` | | | | | Done | Sep 1, 2021 | Oct 27, 2021 | | |
| | Add a `exit.sh` script to the RISCV disk image | | | | | Done | Sep 1, 2021 | Oct 27, 2021 | | |
| | Create RISCV boot-exit tests | | | | | Unresolved | Sep 1, 2021 | Oct 27, 2021 | | |
| | Setup the RISCV disk image to run `m5 readfile` after booting | | | | | Done | Sep 1, 2021 | Oct 27, 2021 | | |
| | Child process of m5.fork() cannot simulate with separate event queues | | | | | Unresolved | Sep 1, 2021 | Sep 7, 2021 | | |
| | Alter the RISCV disk image resource to auto-login on boot | | | | | Done | Sep 1, 2021 | Oct 27, 2021 | | |
| | The RISCV disk image does not contain m5 utilities | | | | | Done | Sep 1, 2021 | Oct 27, 2021 | | |
| | readlink system call has bad interaction with automatic redirects in se.py | | | | | Unresolved | Aug 30, 2021 | Aug 30, 2021 | | |
| | 32 bit syscalls cause segfault | | | | | Done | Aug 30, 2021 | Oct 13, 2021 | | |
| | The hdf5 test assumes the existance of `build/ARM/configs`, which is not the case prior to building ARM/gem5.opt | | | | | Unresolved | Aug 25, 2021 | Aug 25, 2021 | | |
| | Break up cxx_config/init.cc. | | | | | Unresolved | Aug 20, 2021 | Aug 20, 2021 | | |
| | Fix building --with-cxx-config when USE_SYSTEMC=0. | | | | | Unresolved | Aug 20, 2021 | Aug 20, 2021 | | |
| | Update RISC-V platform's I/O device declarations | | | | | Unresolved | Aug 19, 2021 | Aug 19, 2021 | | |
| | Use tags instead of if GetOption('with_cxx_config') to guard cxx config source files. | | | | | Unresolved | Aug 18, 2021 | Aug 18, 2021 | | |
