| | Is instruction-level profiling possible with gem5 simulation? | | | | | Done | Nov 21, 2021 | Nov 28, 2021 | | |
| | Don't reference the specific BaseSimpleCPU type in the SimpleThread::htmAbortTransaction method | | | | | Done | Oct 25, 2021 | Nov 30, 2021 | | |
| | Is gem5 importable from python? | | | | | Done | Oct 8, 2021 | Oct 18, 2021 | | |
| | Gem5 tests don't seem to check the return code of the simulation | | | | | Done | Sep 28, 2021 | Oct 27, 2021 | | |
| | Implement POSIX syscalls with "at" suffix | | | | | Done | Sep 28, 2021 | Oct 13, 2021 | | |
| | ARM SE mode: Cannot access file (RISCV runs OK) | | | | | Done | Sep 20, 2021 | Oct 12, 2021 | | |
| | scons failed to buiild gem5 before git-hooks installed | | | | | Done | Sep 18, 2021 | Sep 18, 2021 | | |
| | DerivO3CPU model hangs when resume from a checkpoint | | | | | Done | Sep 12, 2021 | Sep 29, 2021 | | |
| | KVM to Timing CPU switching does not function properly in the gem5 library | | | | | Done | Sep 10, 2021 | Sep 22, 2021 | | |
| | The X86 boot exit test should be refactored to run any command on boot, not just `m5 exit` | | | | | Done | Sep 1, 2021 | Oct 27, 2021 | | |
| | Add a `exit.sh` script to the RISCV disk image | | | | | Done | Sep 1, 2021 | Oct 27, 2021 | | |
| | Setup the RISCV disk image to run `m5 readfile` after booting | | | | | Done | Sep 1, 2021 | Oct 27, 2021 | | |
| | Alter the RISCV disk image resource to auto-login on boot | | | | | Done | Sep 1, 2021 | Oct 27, 2021 | | |
| | The RISCV disk image does not contain m5 utilities | | | | | Done | Sep 1, 2021 | Oct 27, 2021 | | |
| | 32 bit syscalls cause segfault | | | | | Done | Aug 30, 2021 | Oct 13, 2021 | | |
| | Questions about gem5 RISC-V vector model configuration file | | | | | Done | Aug 16, 2021 | Aug 21, 2021 | | |
| | gem5 version v21 FS mode bring up multi-core failed | | | | | Done | Aug 13, 2021 | Aug 13, 2021 | | |
| | "maxEntryCount" datatype is too shallow for larger LLC and multicore | | | | | Done | Aug 8, 2021 | Aug 9, 2021 | | |
| | Fix some ISA specific ifdefs in the minor CPU. | | | | | Done | Jul 25, 2021 | Aug 4, 2021 | | |
| | Eliminate THE_ISA_STR and find an alternative for checkpoint files | | | | | Done | Jul 25, 2021 | Jul 31, 2021 | | |
| | Eliminate the arch/locked_mem.hh header file. | | | | | Done | Jul 25, 2021 | Sep 28, 2021 | | |
| | Eliminate the arch/page_size.hh switching header file. | | | | | Done | Jul 25, 2021 | Oct 22, 2021 | | |
| | Eliminate the arch/pcstate.hh switching header file. | | | | | Done | Jul 25, 2021 | Nov 30, 2021 | | |
| | Failed to boot Linux using gem5-RISCV | | | | | Done | Jul 14, 2021 | Jul 25, 2021 | | |
| | Error when calling bits function in ARM HTM Checkpoint | | | | | Done | Jul 12, 2021 | Jul 13, 2021 | | |
| | SimpleNetwork does not fully support virtual networks | | | | | Done | Jul 8, 2021 | Nov 30, 2021 | | |
| | Upstream 64-bit POWER SE | | | | | Done | Jul 7, 2021 | Jul 7, 2021 | | |
| | Support for Linux kernel arm64 v5.11+ with PAN enabled. | | | | | Done | Jul 7, 2021 | Jul 8, 2021 | | |
| | Protobuf compile failure on Ubuntu 21.04 | | | | | Done | Jul 7, 2021 | Jul 20, 2021 | | |
| | The Components Library X86 board's I/O subsystem is hardcoded. This should be fixed. | | | | | Done | Jul 6, 2021 | Aug 27, 2021 | | |
| | The Components Library X86 board is hardcoded to 3GB of memory. This should be fixed | | | | | Done | Jul 6, 2021 | Aug 27, 2021 | | |
| | hdf5 stats are broken in 21.0.1 | | | | | Done | Jul 6, 2021 | Jul 7, 2021 | | |
| | gem5 failed to compile on RISCV with systemc enabled | | | | | Done | Jul 5, 2021 | Jul 6, 2021 | | |
| | TimingSimpleCPU fails to compile for POWER | | | | | Done | Jul 3, 2021 | Jul 14, 2021 | | |
| | KVM Mode does not function in the Component Library SimpleProcessor. | | | | | Done | Jul 1, 2021 | Oct 26, 2021 | | |
| | Figure out how best to distribute the gem5 compents library with gem5 | | | | | Done | Jul 1, 2021 | Sep 29, 2021 | | |
| | Add functionality to the components library to download from gem5 resources | | | | | Done | Jul 1, 2021 | Sep 22, 2021 | | |
| | Improve the documentation for `components_library/cachehierarchies/ruby/caches` | | | | | Done | Jul 1, 2021 | Aug 27, 2021 | | |
| | gem5 failed to compile on RISCV (HiFive Unmatched board, Ubuntu 21.04) | | | | | Done | Jun 29, 2021 | Jul 12, 2021 | | |
| | syscall mincore fatal when using miopen in gem5 docker image | | | | | Done | Jun 27, 2021 | Jul 8, 2021 | | |
| | RISC-V vector extension official support plan inquiry | | | | | Done | Jun 17, 2021 | Jun 24, 2021 | | |
| | AddrRangeMap::find algorithm fails for certain interleaved address ranges | | | | | Done | Jun 17, 2021 | Jun 28, 2021 | | |
| | Heap use-after-free bug in mem_ctrl.cc | | | | | Done | Jun 16, 2021 | Jun 29, 2021 | | |
| | Fails to build with scons 4 | | | | | Done | Jun 8, 2021 | Jun 8, 2021 | | |
| | X86 ISA failing to compile in GCC 5 | | | | | Done | Jun 4, 2021 | Sep 21, 2021 | | |
| | Segementation fault while running simple example from the tutorial | | | | | Done | Jun 2, 2021 | Jun 3, 2021 | | |
| | CHI Cache_Controller::functionalRead() never reads clean cache data | | | | | Done | May 28, 2021 | Jun 10, 2021 | | |
| | "--redirects" option doesn't work in for se.py | | | | | Done | May 27, 2021 | Jul 19, 2021 | | |
| | RubySystem::functionalRead with partial data support | | | | | Done | May 27, 2021 | Jun 10, 2021 | | |
| | gem5 failed to build with ‘SLICC_HTML=True’ in v21.0 | | | | | Done | May 26, 2021 | May 28, 2021 | | |
