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Bug
x86 Locked Read-Modify-Write broken with classic caches and multiple timing cores
Unassigned
Austin Harris
High
Unresolved
Oct 21, 2021
Oct 21, 2021
Task
Migrate configs from gem5 resources to configs/example/gem5_library/; translate to use the gem5 library
Unassigned
Bobby Bruce
Medium
Unresolved
Oct 19, 2021
Oct 20, 2021
Task
Create an ISA-agnotic method to obtain gem5 resource from the gem5 library
Unassigned
Bobby Bruce
Medium
Unresolved
Oct 14, 2021
Oct 14, 2021
Task
Boards currently have the linux kernel `root` parameter hardcoded. This is not always correct. Come up a solution for this
Unassigned
Bobby Bruce
Medium
Unresolved
Oct 13, 2021
Oct 21, 2021
New Feature
Is gem5 importable from python?
Unassigned
david mlw
Medium
Done
Oct 8, 2021
Oct 18, 2021
Bug
Fix-sized MessageBuffer delayed enqueuing behaves unexpectedly
Unassigned
Gabriel Busnot
Medium
Unresolved
Oct 8, 2021
Oct 8, 2021
Bug
Gem5 tests don't seem to check the return code of the simulation
Unassigned
Davide Basilio Bartolini
Highest
Unresolved
Sep 28, 2021
Oct 5, 2021
Improvement
Implement POSIX syscalls with "at" suffix
Unassigned
Giacomo Travaglini
Medium
Done
Sep 28, 2021
Oct 13, 2021
Epic
Model DVM messages for TLBIs and DSBs accurately on Arm
Unassigned
Samuel Stark
Medium
Unresolved
Sep 24, 2021
Oct 4, 2021
Task
Improve and expand the resources.json file in the gem5 resources repository
Unassigned
Bobby Bruce
Medium
Unresolved
Sep 23, 2021
Sep 23, 2021
Bug
CHI assertion error when L2 Cache configured as shared cache
Unassigned
Javed Osmany
Medium
Unresolved
Sep 23, 2021
Sep 23, 2021
Improvement
Update gem5's option parser in python/m5/main.py and python/m5/options.py to argparse
Unassigned
Gabe Black
Medium
Unresolved
Sep 20, 2021
Sep 20, 2021
Bug
ARM SE mode: Cannot access file (RISCV runs OK)
Unassigned
Rohit Singh
Medium
Done
Sep 20, 2021
Oct 12, 2021
Improvement
Add support on glibc2.33 systemcall newfstatat()
Unassigned
Apo Knight
Medium
Unresolved
Sep 18, 2021
Sep 21, 2021
Bug
scons failed to buiild gem5 before git-hooks installed
Unassigned
Hoa Nguyen
Medium
Done
Sep 18, 2021
Sep 18, 2021
Bug
gem5art-run check_failure feature limitations with celery
Unassigned
Austin Harris
Medium
Unresolved
Sep 15, 2021
Sep 16, 2021
Bug
kernel panic when restore DerivO3CPU with KVM checkpoint
Unassigned
liyichao
High
Unresolved
Sep 14, 2021
Sep 17, 2021
Improvement
Eliminate use of TARGET_ISA in SCons.
Unassigned
Gabe Black
Medium
Unresolved
Sep 14, 2021
Sep 14, 2021
Bug
DerivO3CPU model hangs when resume from a checkpoint
Unassigned
Luming Wang
Highest
Done
Sep 12, 2021
Sep 29, 2021
Bug
KVM to Timing CPU switching does not function properly in the gem5 library
Unassigned
Austin Harris
Medium
Done
Sep 10, 2021
Sep 22, 2021
Bug
The PARSEC benchmark tests fail for MESI_TwoLevel [gem5 library]
Unassigned
Bobby Bruce
Medium
Unresolved
Sep 7, 2021
Sep 7, 2021
Task
Merge the gem5art library into the more general "gem5 library" (formallly "gem5 components")
Unassigned
Bobby Bruce
Medium
Unresolved
Sep 3, 2021
Sep 3, 2021
Task
Add default value for `Root.sim_quantum`
Unassigned
Bobby Bruce
Low
Unresolved
Sep 3, 2021
Sep 3, 2021
Task
The X86 boot exit test should be refactored to run any command on boot, not just `m5 exit`
Unassigned
Bobby Bruce
Medium
Unresolved
Sep 1, 2021
Sep 1, 2021
Task
Add a `exit.sh` script to the RISCV disk image
Unassigned
Bobby Bruce
Medium
Unresolved
Sep 1, 2021
Sep 1, 2021
Task
Create RISCV boot-exit tests
Unassigned
Bobby Bruce
Medium
Unresolved
Sep 1, 2021
Sep 22, 2021
Task
Setup the RISCV disk image to run `m5 readfile` after booting
Unassigned
Bobby Bruce
Medium
Unresolved
Sep 1, 2021
Sep 1, 2021
Bug
Child process of m5.fork() cannot simulate with separate event queues
Unassigned
Austin Harris
Medium
Unresolved
Sep 1, 2021
Sep 7, 2021
Task
Alter the RISCV disk image resource to auto-login on boot
Unassigned
Bobby Bruce
Medium
Unresolved
Sep 1, 2021
Sep 1, 2021
Bug
The RISCV disk image does not contain m5 utilities
Unassigned
Bobby Bruce
Medium
Unresolved
Sep 1, 2021
Sep 1, 2021
Bug
readlink system call has bad interaction with automatic redirects in se.py
Unassigned
Jason Lowe-Power
Lowest
Unresolved
Aug 30, 2021
Aug 30, 2021
Bug
32 bit syscalls cause segfault
Unassigned
Jason Lowe-Power
Medium
Done
Aug 30, 2021
Oct 13, 2021
Bug
The hdf5 test assumes the existance of `build/ARM/configs`, which is not the case prior to building ARM/gem5.opt
Unassigned
Bobby Bruce
Medium
Unresolved
Aug 25, 2021
Aug 25, 2021
Improvement
Break up cxx_config/init.cc.
Unassigned
Gabe Black
Medium
Unresolved
Aug 20, 2021
Aug 20, 2021
Improvement
Fix building --with-cxx-config when USE_SYSTEMC=0.
Unassigned
Gabe Black
Medium
Unresolved
Aug 20, 2021
Aug 20, 2021
Task
Update RISC-V platform's I/O device declarations
Unassigned
Jason Lowe-Power
Low
Unresolved
Aug 19, 2021
Aug 19, 2021
Improvement
Use tags instead of if GetOption('with_cxx_config') to guard cxx config source files.
Unassigned
Gabe Black
Medium
Unresolved
Aug 18, 2021
Aug 18, 2021
Improvement
Instead of iterating over SimObject.sim_objects and SimObject.enums, declare these actions when SimObject() is called.
Unassigned
Gabe Black
Medium
Unresolved
Aug 18, 2021
Aug 21, 2021
Improvement
Move code in src/SConscript from using the raw Command builder into customized/named builders.
Unassigned
Gabe Black
Medium
Unresolved
Aug 18, 2021
Aug 18, 2021
Improvement
Pull build related code out of the SimObject python class
Unassigned
Gabe Black
Medium
Unresolved
Aug 18, 2021
Aug 19, 2021
Improvement
Questions about gem5 RISC-V vector model configuration file
Unassigned
Minho Ha
Highest
Done
Aug 16, 2021
Aug 21, 2021
Bug
gem5 version v21 FS mode bring up multi-core failed
Unassigned
chen boya
Medium
Done
Aug 13, 2021
Aug 13, 2021
Bug
`build/X86/base/compiler.hh:160:44: warning: 'deprecated' attribute directive ignored [-Wattributes] #new_namespace "'") old_namespace { \` when compiling on stable
Unassigned
Bobby Bruce
Medium
Unresolved
Aug 10, 2021
Sep 7, 2021
Bug
"maxEntryCount" datatype is too shallow for larger LLC and multicore
Unassigned
Majid Jalili
Medium
Done
Aug 8, 2021
Aug 9, 2021
Bug
gem5 failed to compile MinorCPU and O3CPU without also compiling any of the Simple CPUs
Unassigned
Hoa Nguyen
Medium
Unresolved
Aug 4, 2021
Aug 19, 2021
Improvement
Fix some ISA specific ifdefs in the minor CPU.
Unassigned
Gabe Black
Medium
Done
Jul 25, 2021
Aug 4, 2021
Improvement
Update generic config scripts to allow selecting an ISA
Unassigned
Gabe Black
Medium
Unresolved
Jul 25, 2021
Jul 25, 2021
Improvement
Make specifying supported ISA/CPU pairs more explicit.
Unassigned
Gabe Black
Medium
Unresolved
Jul 25, 2021
Jul 25, 2021
Improvement
Make scons able to build multiple ISAs at a time
Unassigned
Gabe Black
Medium
Unresolved
Jul 25, 2021
Jul 25, 2021
Improvement
Eliminate THE_ISA_STR and find an alternative for checkpoint files
Unassigned
Gabe Black
Medium
Done
Jul 25, 2021
Jul 31, 2021
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